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PLL locking

Question asked by Mira Roytman on Jan 5, 2016
Latest reply on Jan 6, 2016 by jeremyzhou

Hi, all

My question is about PLL locking:

I work with CORTEX K70 and our card design is a bit different from evaluation board ( "Tower").

We work from internal clock and use oscillator 1 and PLL1 instead of oscillator 0.

Sometimes PLL stay not locked in despite of lock bit setting (MCG  S2 register) or , may be, losses  it.

Did you have similar problem and how did you solve it?