My Processor Expert K20 project uses Codewarrior for MCU version 10.6.
1. The DMA_LDD component attached is meant to generate a DMA transfer completion interrupt, for DMA channels 0 and 16. The PE generated code erroneously passes the User Data pointer for DMA channel 0 to the ISR, when it should reference DMA channel 16 instead.
2. The DMA completion interrupt stops after a while if both DREQ and INTMAJOR bits are set in the DMA TCD. However if the DMA is left enabled after transfer completion, the interrupt is never lost. Could this be caused by a hardware race condition where the disable request stops the interrupt being generated?
3. My application needs a large number of hardware DMA triggers, but the sub family reference manual K20P144M120SF3RM says a trigger source should not be used to trigger more than one DMA channel, as it could cause "unpredictable behaviour". I have tested using one FTM channel to trigger multiple DMA channels and did not find any problems. Exactly what is meant by "unpredictable behaviour" in this case?
Original Attachment has been moved to: DMA1.c.zip
Original Attachment has been moved to: DMA1.h.zip