How can be calculated the MIPS/MHz ratio of the P4080 processor ? (@ 1200 or 1500 MHz)
Please note that MIPS/MHz ratio is a constant.
For the e500mc core it is about 2.5 DMIPS/Mhz.
And now two things are;
1) the e500mc is capable of:
SP FP = 1 OP/cycle
DP FP = 0.5 OP/cycle
2) ECC is not implemented.
The L1 caches have:
— Instruction cache: 1 parity bit per word of instruction, 1 bit of parity per tag
— Data cache: 1 parity bit per byte of data, 1 bit of parity per tag
Refer to the e500mc Core Reference Manual:
Does P4080 processor support vector floating- point operations ? So , does it use AltiVec technology ?
Please refer to the E500MCRM, e500mc Core Reference Manual:
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