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Instability of K64F ADC calibration

Question asked by FRED WEDEMEIER on Dec 29, 2015
Latest reply on Sep 13, 2017 by manfredschnell

I've attached a histogram showing 6 runs of taking 10,000 ADC readings and plotting ADC count against number of occurrences of each count. Hardware is a FRDMK64F, and the voltage being read is the K64 internal Vref divided by a resistor divider to ground. Each run is preceded by an ADC calibration using the procedure supplied with Freescale sample code. Each individual run looks good: ~13 usable bits which is what I'd expect from a proto board with no optimization of the analog chain.


The stability between runs is not good. There's a spread of more than 64 ADC counts, meaning only 10 usable bits.


My thinking is the ADC readings are stable to +/- 4 ADC counts, so calibration (the peaks of the histograms) should be stable to +/- 4 ADC counts as well.


1. What's the source of this instability?

2. How can this be minimized?

3. Is calibration supposed to be invariant? The reason for asking is that the docs mention saving the calibration values to non-volatile memory and restoring them at boot time - Which seems to imply the values are not voltage or temperature dependent.