Hi, I would like to confirm the JTAG debug interface for MK22FN512VLH12.
Following is a snippet of schematic that has worked in the past for K60-based controllers, but this is a new chip for us, so I want to make sure.
I verified with "Debug interface.pdf" which was kindly posted to this forum by Ping in August of this year (2015), but the document does not specify the strength of the pullup/down resistors, nor the direction, for all three pins in question.
Fortunately, the document does specify that pin 10 of the JTAG connector goes to the microcontroller main reset.
The 3.3V I think is used as reference for the JLink adapter, so it goes *out* of my PCB, whereas of course the pins 11 and 13 come *into* the PCB.
The MCU_RESET signal has a 10k pullup elsewhere in the schematic, not shown here.
Therefore, following questions:
Thank you very much
Michael
Hi Michael,
1> There is a document <Kinetis Peripheral Module Quick Reference> includes debug interface circuit design at chapter 2.1.5.3 (page 32) .
The pull up/down resistor application at the debugger interface circuit should be correct.
2> The K22 supports external 50MHz clock input as clock source at EXTAL0 pin.
3> Please download FRDM-K22F schematics from here.
4> Besides of <Kinetis Peripheral Module Quick Reference> document, customer could refer Kinetis Hardware design Tip& Tricks document from below link:
Kinetis Hardware Design Tip & Tricks
5> Unfortunately, there is no K22F checklist.
Wish it helps.
best regards,
Ma Hui
Thank you very much.