External SDRAM maxmam density of Vybrid.

[takashitakahash]

Hi community.

Our customer has below questions.

· What is the SDRAM density upper limit of Vybrid?

Also, please tell me if there is a restriction.

- Would you Please reference layout connect to SDRAM and Vybrid.

- Attached is an excerpt of the iMX6 dual  circuits.

I wired it the same as?

- Please tell me the way if i want to use two by switching the DDR SDRAM.

Best Regards.

[richard_stulens]

Hi Takashi -san,

Vybrid supports a maximum of 1 GB of SDRAM.

It has a 16-bit wide data bus, so we recommend to use a single 16-bit device for easy layout.

Please refer to the hardware developers guide for layout information. You can re-use the DDR layout of the tower or EVB boards.

These boards have a DDR layout that does not require termination resistors and we have correct DDR controller configuration for this layout.

You can find the hardware develpers guyde and more information at:

VF6xx MPUs with ARM Cortex-A5/M4 Core|Vybrid|NXP

Best regards,

Richard

[takashitakahash]

Hi Richard.

Thank you for your reply.

I read VYBRID RM of section 3.7.2.1. DDR maximum address space.

There are described on "  As a result, the maximum accessible memory area is 1Gbyte(125MBit).

But , On the other , in Table4-1 are described on allow 2GB accessible below.

------------------------------------------------------------------------------------------------------------------------------------------------- 

                                                Table 4-1. Device Memory Map

CM4 Address Range                          Size          CM4 Alias              System Address (A5)         Region Description               

[Start Addr - End                                 [MB]                [Start Addr - End

Addr]                                                                                              Addr]                      

----------------------------------------------------------------------------------------------------------------------------------------------------

0x8000_0000-0xdfff_ffff                    1536                           0x8000_0000-0xdfff_ffff                            DDR

0xe000_0000-0xffff_ffff                      512               N/A                   Reserved                          CM4 Private Periphera                                                                                                                                                       Bus (PPB                                                  512                N/A        0xe000_0000-0xffff_ffff                       DDR (A5 only)

-------------------------------------------------------------------------------------------------------------------------------------------------------

Question.

Table 4-1  of Device memory map has been described on   0x8000_0000 ~ 0xdfff_ffff,  0xE000_0000 ~ 0xffff_ffff (A5 only),

Since the maximum 1Gbit only available,It is the memory 0x8000_0000 ~ 0xbfff_ffff that can be used.

Is it correct?

Thanks,

Best.

T.Takahashi

[jiri-b36968 · Accepted solution]

Hello Takashi-san,

main DRAM memory space is mapped from 0x8000_0000 to 0xFFFF_FFFF. (2GB)

It can be used directly by Cortex-A5 only. Cortex-M4 has PPB from 0xE000_0000.

Cortex_M4 can address from 0x8000_0000 to 0xDFFF_FFFF. (1.5GB)

Cortex_M4 also can use alias from 0x0080_0000-0x0FFF_FFFF to eliminate wait state (248MB)

Maximal address space is no. of CS x 2^Address x no.banks x datapathwidth

= 1 x 2^ (11 COLs + 16 ROWs) x 8 x 2 = 1 x 128MB x 8 x 2 = 2GB for 16 bit interface

= 1 x 2^ (11 COLs + 16 ROWs) x 8 x 1 = 1 x 128MB x 8 x 1 = 1GB for 8 bit interface

On reference platform are used only signals col 0-9, row 0-12 -> 1 x 2^23 x 8 x 2 = 128MB (1Gb) (K4B1G1646G-BCF8).

In this case we use range 0x8000_0000 to 0x87FF_FFFF

/Jiri