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understanding iomuxing imx6QD

Question asked by srinivasaporam on Dec 24, 2015
Latest reply on Apr 25, 2017 by glitch911

Hi,

We are working on imx6q processor board and want to understand iopin muxing in detail. for this we have refereed to imx6q-pinfun.h file

 

for example: it states:

 

#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC   0x25c 0x62c 0x000 0x0 0x0
#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1         0x25c 0x62c 0x000 0x3 0x0
#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x25c 0x62c 0x000 0x5 0x0
#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL     0x25c 0x62c 0x000 0x7 0x0

 

where it staed that  the pin function ID is a tuple of

<mux_reg      conf_reg      input_reg      mux_mode       input_val>

 

if i take one example from above let's say :

 

#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1     0x25c 0x62c 0x000 0x3 0x0

 

if i look the reference manual, then mux-reg for CSI0_MCLK is IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC (Address: 20E_0000h base + 25Ch offset = 20E_025Ch) offset is 0x25c

 

conf_reg for CSI0_MCLK is IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC (Address: 20E_0000h base + 62Ch offset = 20E_062Ch), so offset is 0x62c

 

MUX-Mode i need select from IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC whose value 011 (0x3)

 

So

#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0

 

in above macro i got 0x25c 0x62c 0x3 but what about values of  input_reg (0x000) and input_val (0x0) ??????? how to get them correctly?????

 

 

and also if iam using them in my dts for iomux

 

for example say :

 

mipi_csi {

        pinctrl_mipi_csi_1: mipi_csipgrp-1 {

            fsl,pins = <

              

                    MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1    0xb0b1

 

            >;

        };

 

};

 

in above 0xb0b1 is the value taken from IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC.

 

which is the value we should take. is taking SW_PAD_CTL_PAD value be sufficient?????

 

 

Please reply...

 

 

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