How to check whether the data transfer was completed, with FEC of i.MX25.

[yuuki]

Dear all,

In FEC of i.MX25, would you tell me about a method to check that data transfer was completed?

We refer to the following point of the reference manual.

25.5.2.1 Driver/DMA Operation with Buffer Descriptors (P.850)
-----
"After the data DMA is complete and the buffer descriptor status bits have been

written by the DMA engine, the RxBD[E] or TxBD[R] bit is cleared by hardware to

signal the buffer has been “consumed.” Software can poll the BDs to detect

when the buffers have been consumed or can rely on the buffer/frame interrupts."
-----

According to this, we understand there is two methods to check the data transfer of FEC was completed.

A) SW polls it until TxBD[R] is cleared.
B) SW relies on the buffer/frame(EIR[TXF]) interrupts.

The frame may be constructed in a number of Buffers.
However, in the Linux BSP_FEC driver of NXP, one frame is constructed by one buffer.

===================================
　static status_t xio_write( XCONTAINER* x_contnr, void*buffer, size_t length )
　→
　status_t WriteFrame( CTB_LAN* control, void* buffer, size_tlength )
　→
　static status_t SendBuf( CTB_LAN* control, void* data, size_tsize )
===================================

We used a method of (A).
However, we were not able to detect transfer completion correctly.

When a method of (B) is used, it seems that we are able to detect transfer completion correctly.

We do not understand difference between (A) and (B).
We want to know the reason that we cannot detect correctly by (A).

May I have advice?

Best Regards,
Yuuki

[Yuri]

Hello,

The event EIR[TXF] means the whole frame (which may contain several TxBDs
and buffers) is sent. The event TxBD[R] cleared (after being set) means, that

only single buffer has been sent. Generally EIR[TXB] should be also set in such case.

  Note, FEC Buffer Descriptors (BD) are described as following :

typedef struct BufferDescriptor

{

    U16 length;      // transfer length  - this field is Low Significant 16-bit field of 32-bit word

    U16 cstatus;     // control and status - Most Significant 16-bit field

    U32 addr;        // buffer address

}BD;

  Please pay attention, the first structure field is length, not status as it is

described in the Reference Manual. This is because of little endian mode of the

ARM core. 

There are requirements for FEC BD ring and buffers to be properly aligned :

BD ring should 128-bit aligned, receive data buffers 16-bytes aligned, transmit

buffers - 32-bit aligned.

Have a great day,
Yuri

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[yuuki]

Thank you for your quick reply.

We would like to ask an additional question.

Previously we confirmed it by polling if TxBD[R] was cleared because a frame had only one BD.
However we found an issue that ethernet packet was not sent although TxBD[R] was cleared.

So we modified the driver to confirm the sending completion by receiving interrupt with EIR[TXF].
After that, the issue does not occur.

Eventually should we confirm the sending completion by receiving interrupt with EIR[TXF] though our sending frame has only one BD ?

Best Regards,

Yuuki

[Yuri · Accepted solution]

Hello !

  You wrote " that ethernet packet was not sent although TxBD[R] was cleared".

This may take place, when the TxBD was processed, but data was not sent yet

because of internal FIFO. 

Regards,
Yuri.