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About EIM burst access in i.MX6SL.

Question asked by Keita Nagashima on Dec 21, 2015
Latest reply on Dec 21, 2015 by Yuri Muhin

Dear All,

 

Hello. I have questions about EIM burst access in i.MX6SL.

My customer will connect the FPGA via EIM on custom board and want to fix the FPGA's output timing.

 

[Q1] About Burst Read Memory Accesses

Refer to "20.8.7 Burst (Synchronous Mode) Read Memory Accesses Timing Diagram - BCD=0" in i.MX 6SoloLite Applications Processor Reference Manual, Rev. 2, 06/2015.

 

Is my below understanding right?

- Latch timing of control signals by FPGA is rising edge of BCLK.

- Output read data timing is falling edge of BCLK.

 

[Q2] About Burst Write Memory Accesses

Refer to "20.8.9 Burst (Synchronous Mode) Write Memory Access Timing - BCD=1" in i.MX 6SoloLite Applications Processor Reference Manual, Rev. 2, 06/2015.

Is my below understanding right?

- Latch timing of all signals (control & data) by FPGA is rising edge of BCLK.

 

[Q3]

I think that the register to select the BCLK polarity (rising or falling) doesn't exist in i.MX6SL.

Is it right?

 

Best Regards,

Keita

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