Looking at the SPI signals, there are brief mentions of SPI0_PCS5 in the multiplexing table (table 10.3.1) in the MK10DN512VLL10 reference manual, version 2. Is there really a SPI0_PCS5 signal? The chapter for the SPI module only shows SPI0_PCS0-SPI0_PCS4, however the SPI_PUSHR register shows PCS[5:0]. Possibly this is a holdover from the MK10DN512ZVLL10 part?
Another question, the features for the SPI mention possibly using an external mux to expand the SPI strobe signals. I'm assuming this means that when doing a SPI transfer, the PCS[5:0] can have multiple bits asserted, so that one pin can drive an enable on a decoder while others are driving the decoder inputs. Is this correct? Expanding on that, is there a way to ensure the enable line is asserted after the decoding bits?