Hello,
To use the QD2 for the IR encoder application, you would need to write your own code. Since there is no CMT, the carrier would need to be generated by other means - there are a couple of possibilities.
But first, let's examine the characteristics of the RC5 format, to get a better idea about the timing considerations required. The QD2 device is capable of generating nominal bus frequencies of 8MHz, 4MHz, 2MHz or 1MHz. I will assume "standard" trimming to exactly these frequencies.
The RC5 carrier requires a frequency of 36kHz, with about 30 percent duty. For a 4MHz bus, each carrier cycle would occupy exactly 111 bus cycles, possibility with an ON period of 34 cycles, and an OFF period of 77 cycles. For 8 MHz bus, the number of cycles will double.
Each burst of carrier may be either 32 or 64 carrier cycles. The gap between carrier bursts will correspond with 3556 or 7111 bus cycles, assuming 4 MHz.
The first possibility -
- Use a timed firmware loop to generate each carrier cycle. The loop must provide the number of cycles required for the correct carrier frequency, and must also test for when the carrier burst is complete. Interrupts must not occur while the burst is being generated. This would also imply that the firmware must be coded in assembler.
- Use a TPM channel, with software only output compare mode, to time the gap between carrier bursts. In this case, the interrupt would probably be used.
This method should be feasible for a bus frequency of 4MHz. "Padding" cycles will probably be needed within the loop, to adjust the timing.
The second possibility -
It would be tempting to consider whether the TPM channel could also be used to generate the carrier signal, in addition to the gap period, this time using the channel hardware output pin to directly switch the IRED driver transistor.
This will require the processing of the ISR within a worst case period of 34 bus cyles, for 4MHz. I doubt that this is feasible. However, for 8 MHz bus, the worst case period would be 68 bus cycles, which might just be feasible, with very careful coding, again in assembler. No other interrupts, except the timer channel interrupt, should be enabled during the carrier burst period.
Regards,
Mac