AnsweredAssumed Answered

i.MX6SoloX Stop mode

Question asked by David JAOUEN on Dec 16, 2015
Latest reply on Dec 22, 2015 by David JAOUEN



I'm trying to set the i.MX6SX into Stop mode.

I use a i.MX6SoloX Sabre SD board. The software boots U-Boot on QSPI2.


I use U-Boot to load software in OCRAM and start it (no Linux OS loaded):

=> tftpboot 0x00900000; dcache off; go 0x00900000


Here is the piece of code (executing on Cortex-A9):

int main(int argc, char **argv)


    CCM_MemMapPtr ccm = (CCM_MemMapPtr)CCM_BASE_ADDR;

    PGC_MemMapPtr pgc = (PGC_MemMapPtr)GPC_BASE_ADDR;


    ccm->CLPCR    = (ccm->CLPCR & ~CCM_CLPCR_LPM_MASK) | 0x02;  // Set the LPM bits to Stop mode 

    ccm->CCR      = ccm->CCR      | CCM_CCR_RBC_EN_MASK;        // Set RBC_EN bit in CCM_CCR register

    pgc->CPU_CTRL = pgc->CPU_CTRL | PGC_CPU_CTRL_PCR_MASK;      // Set PCR bit in PGC_CPU_CTRL register


    __asm volatile ("wfi");                                     // Should enter Stop mode



    return 0;



The problem is that when executing the WFI instruction, the i.MX6SX is reset. U-Boot shows the reset was caused by a watchdog time-out.

When RBC_EN bit is not set, the Cortex-A9 enters in wait for interrupt state but the whole chip does not enter in Stop mode.


So, what am I missing to enter the chip in Stop mode?





PS1: I know there is other operations to do to wake up properly from Stop mode, but this is the next step. For now, I'm just trying to enter into Stop mode.

PS2: I determined the chip mode by tracking the current consumption on VDD_ARM_IN and VDD_SOC_IN supply lines.