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What's the default configuration of CP15:C11:C1:1, PLEPCR, in IMX6 BSP?

Question asked by Dehuan Xin on Dec 16, 2015
Latest reply on Dec 18, 2015 by igorpadykov

I found in <ARM Cortex A8 TRM (ARM DDI 0388F)>, section 4.3.30, <Preload Engine Parameters Control Register>, that "PLE wait states" (PLEPCR[7:0]) can be used to limit the usage of PLD instructions.

 

What's it's reset value or default value in IMX6 BSP? And where shall I place the code that changes it during boot process, in U-BOOT or kernel?

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