Hello,
I have a custom board using the QorIQ T2080 processor. When the board powers up, it appears to complete the power-on reset sequence correctly, but the cores of the T2080 don't have the 'core ready' bit set in the DCFG_CCSR_CRSTSRn registers. This is true for all of the cores. The RCW is loaded via the I2C bus and the register contents are correctly seen in the DCFG_CCSR_RCWSRn registers. I have checked the status of the SerDes PLLs and they are locked and seem to be happy. I can access registers using a emulator via the COP header on the board and that seems to work fine. I just cannot execute any code, which I assume is due to the cores not being ready.
The reference manual states that the 'core ready' bit could be cleared if a core is in the PH10 or PH15 power saving state, but that does not appear to be the case when looking at the RPCM_TPH10SR0 and RPCM_PCPH15SR0 registers.
The problem is seen when performing a power cycle, as well as when performing an emulator reset.
Any insight or suggestions of things to try or look at would be appreciated,
Best regards,
Graham Bardouleau.
Hi Graham Bardouleau,
The reference manual also list a third states for DCFG_CCSR_CRSTSRn[READY], did you check that one:
• Core held in reset via a warm reset from the MPIC
BR
Lunmin