AnsweredAssumed Answered

Strange behavior of epit timer - imx6sx m4 core

Question asked by Alan Casinelli on Dec 11, 2015
Latest reply on Dec 17, 2015 by Alan Casinelli


I'm currenty running some examples from the mqx rtos 4.1.0 for the imx6sx cortex-m4 core. In particular the hwtimer one. I'm able to run them both from OCRAM and DDR though i'm experiencing problems when the timer interrupt is set to frequencies >= 150kHz.


I modified the sample code of the hwtimer example by using only one timer (BSP_HWTIMER1_DEV = epit1) at a frequency of 150kHz and every time the callback is fired, I will toggle a pin of the board. I should expect a periodic waveform of 75kHz period and 50% duty cicle, instead I see a duty cicle of about 85% (or 15% as sometimes the pin seems like not to toggle at all).


The timer displays the right frequency (24MHz when the perclk is derived from the osc) and the Load register displays the right value 0x9f (159/24MHz = 6,625us).


The strangest thing is that if the code is running from the DDR and the a9 boots up, then the waveform duty cicle and period gets corrected to the right ones.

The same doesn't happen if the code is running from the OCRAM.


I've checked the different clocks configurations and they all seems to be equal, except the pll1 which is derived from the step_clk in linux and from the core clock in the m4.


Thanks for your help.


EDIT: I made some more research about how the clocks and frequecies are set in the BSP library.

I switched the perclk to be derived from the ipg and the frequency displayed is 60MHz instead of 66MHz ( the ahb_clk id derived from pll2_pfd2 with a pll2_pfd2_frac = 24; the ahb_podf and ipg_podf are 3 and 2 respectively, so pll2_pfd2=528*18/24MHz=396MHz, ahb=396/3MHz=132MHz and finally ipg=132/2MHz=66MHz)

Also considering how the divider is set, shouldn't the load register get filled with 0xA0 instead of 0x9f, since 24MHz/150kHz=160=0xA0? Or the epit timer needs 1 clock tick to generate the interrupt after the value has been compared?