In the Freescale SDK IPU driver, Display control submodule, the microcode gets written to an area starting in IPU_MEM_DC_MICROCODE_BASE_ADDR. This winds up being 0x02780000 in the system memory map, but I can't find any documentation on this in the datasheet.
Same thing in the display processor section, there are registers like SRM_DP_COM_CONF_SYNC which wind up being at 0x02740000 which again has no documentation. I see mentions of an "IPUv3 Spec". Maybe that's where this stuff is at? Can you point us at this please? Thanks.