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Software MSI generation on P1012

Question asked by masasi on Dec 9, 2015
Latest reply on Dec 23, 2015 by Pavel Chubakov

Hi!

I have two P1012 processors communicating through PCIe. When the EP sends a message to the RC, I want to generate an MSI transaction to the RC.

I have performed the following steps:

1) In the EP, I configure MSI capabilities on the PCI Compatible Device-Specific Configuration Space.

This is the memory dump:

00000040: 00000000 7e024c01 00000000 01017010

00000050: 003c0001 0000281e 0003d441 00110000

00000060: 00000000 00000000 00000000 00000000

00000070: 00890005 fff41740 00000000 000000e0


For the MSI Message Address I configured: PEXCSRBAR+0x4_1740.

In order to know the value of PEXCSRBAR I went to the RC configuration header and the information provided was:        

00000000: 010a1957 00100006 0b200011 00010008

00000010: fff00000 00000000 00010100 00000000

00000020: da00da00 00011001 00000000 00000000

00000030: 00000000 00000044 00000000 00000000


So I set PEXCSRBAR=0xfff00000 and then MSI Message Address=0xfff4_1740. The MSI Message Data=000000e0.

Is this step correct?

 

2) Then I create an Outbound ATMU in the EP with the following information:

     PEXOTAR=0x000fff41

     PEXOTEAR= 0x00000000

     PEXOWBAR=0x000B0000

     PEXOWAR=0x8004400B

Here is the memory dump:

ff70ac00: 00000000 00000000 00000000 00000000

ff70ac10: 80044023 00000000 00000000 00000000

ff70ac20: 000ad000 00000000 000a0000 00000000

ff70ac30: 80044013 00000000 00000000 00000000

ff70ac40: 000ab000 00000000 000a0100 00000000

ff70ac50: 80044013 00000000 00000000 00000000

ff70ac60: 000fff41 00000000 000b0000 00000000

ff70ac70: 8004400b 00000000 00000000 00000000

Is this step correct?

 

3)Finally, on the EP I write to address 0xB0000740(which is the ATMU base address that maps MSIIR register of RC's side) the value 0xE0, I was expecting to see the PIC_MSIR7 set on the corresponding bit but it is always set to 0. What could be the problem with my configuration?

 

Thanks in advance

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