I want to design a solution based on The IMX6.q, which dose data acquisition.
The data acquisition device is FPGA, and the reading and writing speed of data acquisition is 200MB/s.
Now, the FPQA device communicates with IMX6.q through by EIM control.
However, maximum frequency of the EIM main clock is 133Mhz.
My questions are as following:
1.The EIM can support 200MB/s speed?
2.If it's ok, how to design it?(Burst Clock mode + SDMA or not)