Hi Himanshu
ipg_clock is produced from AHB_CLK_ROOT as shown on
Figure 18-5. BUS clock generation http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf
so changes in devicetree are not sufficient. It is necessary to reprogram pll2/3, producing
this clock.
Best regards
igor
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