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i.MX6UL DDR3 Design

Question asked by Ricardo Ferreira on Dec 1, 2015
Latest reply on Dec 9, 2015 by Wouter Stapper



In the i.MX 6UltraLite Evaluation Kit design, the DDR3 the Address, command and control group are not routed in the same plane. I though these signals needed to be in the same plane. The aproach made in the evaluation board make the routing much easier but is it safe?
Is there any special rule I should follow to route some of these signals in different layers?