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Unfamiliar message from freescale tool "ddr_stress_tester_v2.30"

Question asked by Yoshi Tanamura on Dec 2, 2015

(Question)

We are developing our own PCB and we use freescale tool "ddr_stress_tester_v2.30" in order to extract some parameters

for calibration of DDR3 SDRAM interface now. But we receive the following unfamiliar messages from it.

--------------------------------------------------------------------
============================================
        Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00003058
SRC_SBMR2(0x020d801c) = 0x21000001
============================================

ARM Clock set to 800MHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Tempareture: 44
============================================

DDR Freq: 528 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F Write DQS delay result:
   Write DQS0 delay: 31/256 CK
   Write DQS1 delay: 31/256 CK
   Write DQS2 delay: 31/256 CK
   Write DQS3 delay: 31/256 CK

Starting DQS gating calibration
. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration
--------------------------------------------------------------------

 

If anyone knows the cause of this failure, please explain it.
We expect delay value of "MMDC_MPWLDECTRL0/1 ch0" and value of "Write DQS0 delay:"
should be random. But above results are all the same.
We assume calibration does not work correctly.

And also, a voltage of DRAM_RESET signal is mesured about 100 mv which is reset condition.
It seems that calibration doesn't work correctly.

As we can't use DDR3 SDRAM analyzer to our PCB, we can't observe interface directly.

Any advices are helpful.

 

Thank you.

 

Yoshi Tanamura

 

Dec. 3  13:40  JST

 

Hello,

After monitoring PCB, we find out Y6 terminal(DRAM_RESET) is still "L" value

and reset status is not freed. So this should be the cause of failure,

but we don't know how to fix it.

We believe that we operate tool "ddr_stress_tester_v2.30" correctly.
Please let us know why Y6 terminal is still "L" value and how to fix it.

Thanks.

Yoshi Tanamura

 

P.S. I attach our setting file of tool "ddr_stress_tester_v2.30".

Original Attachment has been moved to: ddr_stress_teset_param.inc.zip

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