Helllo John,
I think what you are implying is that the transmission complete flag is set before the receive flag is set , under your specific conditions, probably due to a slight difference in timing within the SCI module. However, should interrupts be globally disabled at the time when both flags become set, I would assume the interrupt priority situation would exist when interrupts were re-enabled, and the receive interrupt would be serviced first.
If this is the situation, an ambiguity can exist for your case. Whether the delay difference is "a few microseconds", or a substantial portion of a bit period, would be an interesting question.
If you require a consistent priority, for example TC, you might first test whether the TC flag is set from within the receive ISR, and process the TC event if so, prior to receive processing. It should be possible to also use this technique to identify the actual amount of delay, by waiting for the receive flag to become set from within the TC ISR, and use the timer count to estimate the delay.
Regards,
Mac