inquiry external clock placement and plan by i.MX6 PCIe GEN2

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inquiry external clock placement and plan by i.MX6 PCIe GEN2

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andychien
Contributor III

Dear Sir,

Our customer would like and  think to feed external clocks into CLK2 pins, then CLK1 output to PCIe device on PCIe GEN2 application.

Below structure.

Please help check is it possible and how to setting it by software.

Thanks,

snap.jpg

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igorpadykov
NXP Employee
NXP Employee

HI Andy

recommended external circuit is given in answer on below link

(Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev2.9.xlsx"))

PCIe REFCLK

also refer to attached patch

Best regards

igor

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andychien
Contributor III

Dear Sir,

Thanks very much for you are checking and provide this patch.

I will pass to customer test.

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