number of clock cycles spent performing division instruction (s12xe) - rephrase

[Xbot]

hi,

i am using codewarrior4 as compiler for S12xe mcu... does anybody know how many clock cycles is spent when performing division (c code)? and does this by any means affect the latency of interrupts?

thanks,

[Xbot]

hi allawtterb,

the document link you provided only has 452 pages. can you please clarify?

[J2MEJediMaster]

It looks like there's a manual versioning problem. Download the S12XCPUV1 reference manual from here:

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV1.pdf?fsrch=1

and check page 210 which has cycle info on the IDIV instruction. HTH.

---Tom

[allawtterb]

Strange, well on the link that JediMaster posted the interrupt recognition information is on page 381 and the table for how many instruction cycles math instructions takes is on page 469.  As bigmac pointed out, your C division will take more than one assembly instruction.  The biggest latency that can be incurred from your C division is the longest instruction that results from that line of code.  You can try to look at the disassembly to determine this but it might include a jump to a special assembly routine to perform the division (especially if it is a 32bit/32bit division).  If you really want to know then just run a full chip simulation and do single assembly steps once you get to the division you are wondering about.  Tha being said,  I would expect that none of these instructions would be longer than 12 instruction cycles though.

[bigmac]

Hello Xbot,

It is likely that your C statement that uses the division process will compile to more than one assembly instruction.  The easiest way to obtain the number of cycles required by the statement is to use full chip simulaton, and single step, noting the cycle count before and after the statement is executed.

Interrupt latency can occur between different assembly instructions, so perhaps you might globally disable interrupts prior to the critical period, and re-enable at the conclusion of this period.

Regards,

Mac

Message Edited by bigmac on 2008-02-07 05:51 PM

[allawtterb]

If an interrupt occurs during the execution of an instruction, the interrupt will only be serviced after the instruction has completed.  This is true expect for certain fuzzy logic commands.  To get a better understanding for how interrupts are recognized for the S12X take a look at section 7.5.3 (Page 385) of the following document. 

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf?fsrch=1

Also in the document is a list of instruction cycles required for math commands, the longest any single assemblyn division command takes is 12 instruction cycles.  Look at page 473 for the list.