In the Rev 2 Datasheet for the P3041, page 133 under clocking ranges specifies a minimum core clock frequency of 400MHz.
However, NOTE 8 applies, which states that for rev1.1 silicon, the core clock frequency must be at least as fast as the platform clock frequency.
The minimum platform clock frequency is specified at 600MHz.
Thus I interpret this to mean that the minimum core clock frequency now jumps up from 400MHz to 600MHz.
HOWEVER, I do not believe the PLL ratio can be setup in order to produce a 600MHz core clock frequency.
Therefore, my final interpretation of the minimum usable core clock frequency leads me to 800MHz.
The intent here is to perform power dissipation and thermal management analyses, in which the P3041 core clock frequency is varied from an unclear minimum frequency to a clear 1.5GHz maximum.
I seek assistance in clarifying the actual usable fully functional minimum core frequency for this device, meaning no functional ramifications in terms of SERDES interfaces or other functional units of the processor. If the absolute minimum core clock frequency (whatever it turns out to be) imposes limits in terms of performance outside raw core processor cycles, such insight would also be greatly appreciated.
Lastly, what about for the Die Revision 2.0 P3041 device -- I see nothing listed in the 2.0 die revision nor the 1.1 die errata -- why does NOTE 8 specifically callout die revision 1.1 then?