I have a case which needs to support dual-display.
The primary display: RGB port output, 1280*720, 60Hz, on ipu1.
The secondary display: LVDS port output, 800*480, 60Hz, on ipu0.
There are 2 clock configurations:
1、pll5 for primary, while pll2 for secondary.
In this case, the expected frequency is 33.264M (800*480, 60Hz), so the PLL2_PFD0 should be 33.263*7=232.8M. But the actual pll2 clock we can configure is 271.5M.
2、pll2 for primary, while pll5 for secondary.
I can get the correct clocks in this case. The problem is :
By changing pll5_video_main_clk to 232M (from original 650M), i can get excepted clocks. The problem is :
pll5_video_main_clk is also source for other ip modules like, ipu1_di_clk.
I wonder whether the new configuration has bad impacts on other modules.