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DDR Stress Tester v1.03 fails with 8Gb DDR3 Memory Chip

Question asked by Richard Milakovich on Nov 25, 2015
Latest reply on Nov 26, 2015 by igorpadykov

Recently I received a new revision of our custom hardware that uses the i.MX6 SoC and the following 8Gb DDR3 Memory Chip.  The hardware uses a 16-bit data bus to interface to the DDR3 Memory Chip.

Micron MT41K512M16HA-125:A

 

Using the "DDR Stress Tester v1.0.3" I successfully ran the DDR calibration on these boards.

However when I run the DDR Stress Test, it fails after running for 2 to 4 hours with the same error each time.

This has happened on 4 different Rev3 Boards, here is the error I see.

loop: ??

DDR Freq: 396 MHz

t0.1: data is addr test

Address of failure: 0x10000000

Data was: 0x00000000

But pattern  should match address

 

Earlier I ran the "DDR Stress Tester v1.0.3" on older Rev2 Boards with the following 4Gb DDR3 Memory Chip and these tests never failed.

Micron MT41J256M16HA-125:E

 

I recently enabled the Alternate Memory Test code in U-Boot and started running this memory test on the Rev3 Boards with the 8Gb DDR3 Memory Chip.

I have run the U-Boot Memory Test for up to 50 hours without any errors.  I have never seen an error using the U-Boot Memory Tests.

 

 

Can I get the source code for the "DDR Stress Tester v1.0.3", or an explanation of the memory tests, so I can understand this error better.

 

I have also tried running the "DDR Stress Tester" v2.00, v2.20, and v2.30 but all of these fail both the DDR Calibration and the DDR Stress Test very quickly.

The DDR Calibration fails as follows.  The DDR Stress Test also fails with a not supported error.

Write leveling calibration completed

 

Starting DQS gating calibration

ERROR: NOT SUPPORTED

 

I read on some of the other i.MX6 Community Pages that the current build of "DDR Stress Tester" v2.xx do not support a 16-bit data bus for the DDR Memory interface.

If this is true, can I get a build of "DDR Stress Tester v2.30" that will work with a 16-bit data bus interface to the DDR Memory?

 

Best Regards,

Richard Milakovich

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