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About i.MX6Q interrupt priority

Question asked by zhq li on Nov 24, 2015
Latest reply on Nov 27, 2015 by zhq li

Dear all,



I have a question about interrupt priority in i.MX6Q.

In IMX6DQRM, chapter 2, table2-1 system memory map it gives us the interrupt controller and interrupt distributor registers' address range, but I cannot find the definition about these registers.

Similarly it only gives us the registers’ address about interrupt priority in BSP, besides there is no useful information to this question.


I wonder how to config interrupt priority.


Best regards.