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inbound PCIE assigned memory size in case of using i.mx6q

Question asked by 徳宇李 on Nov 23, 2015
Latest reply on Nov 25, 2015 by 徳宇李

Hi,

 

I connected  FPGA to i.mx6q on pcie bus and need to access over 128MB memory area.

I found that it seems to be a limit of 15MB for PCIE assigned memory regions under which everything's ok

and over which I get these messages on kernel startup.

 

PCI host bridge to bus 0000:00

pci_bus 0000:00: root bus resource [io  0x1000-0x10000]

pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]

pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]

PCI: bus0: Fast back to back transfers disabled

PCI: bus1: Fast back to back transfers disabled

pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

PCI: bus2: Fast back to back transfers enabled

pci 0000:00:00.0: BAR 8: can't assign mem (size 0xa000000)

pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]

pci 0000:00:00.0: BAR 9: assigned [mem 0x01100000-0x011fffff pref]

pci 0000:00:00.0: BAR 6: assigned [mem 0x01200000-0x0120ffff pref]

pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x1fff]

pci 0000:01:00.0: BAR 8: can't assign mem (size 0xa000000)

pci 0000:01:00.0: BAR 0: assigned [mem 0x01100000-0x0110ffff 64bit pref]

pci 0000:01:00.0: BAR 7: assigned [io  0x1000-0x1fff]

pci 0000:02:04.0: BAR 2: can't assign mem (size 0x4000000)

pci 0000:02:04.0: BAR 3: can't assign mem (size 0x4000000)

pci 0000:02:04.0: BAR 0: can't assign mem (size 0x200)

pci 0000:02:04.0: BAR 1: assigned [io  0x1000-0x10ff]

pci 0000:01:00.0: PCI bridge to [bus 02]i

pci 0000:01:00.0:   bridge window [io  0x1000-0x1fff]

pci 0000:00:00.0: PCI bridge to [bus 01-02]

pci 0000:00:00.0:   bridge window [io  0x1000-0x1fff]

pci 0000:00:00.0:   bridge window [mem 0x01100000-0x011fffff pref]

PCI: enabling device 0000:01:00.0 (0140 -> 0143)

 

I use Inbound PCIE which can access 4GB external memory area in term of

[i.MX 6 Dual/6Quad Applicatiuons Processor Reference Manual].

In default it can access inbound PCIE 15MB memory area in test of result and above document.

I want to know if it possible to access inbound PCIE 129MB memory area by modify source code or other methods.

 

Can someone help me to find a solution?

 

Thank you very much.

 

David

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