I'm attempting to set up SPI transfers on a K22 using PE and the SendBlock function, and I need PCS to be continuously asserted during the transfers. The slave device is slow to wake up, so the PCS to SCK delay has to be relatively high. It appears that each byte is being sent as a separate transmission. I believe that PCS is being de-asserted briefly, but someone borrowed my fast logic analyzer and the one I'm left with won't pick it up. I'd set tDT to extend the time between transfers to be sure, but I can't find tDT anywhere in PE.
I'm seeing a delay between bytes equal to the time I configured for the PCS to SCK delay, and that's the big problem. It makes the transfers very slow, and I can't reduce the delay time without causing wake-up problems for the slave.
1) How do I keep PCS low during a complete block transfer, short of manual GPIO control?
2) Is tDT configurable in PE? I'm going to need it later.