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i.MX6 DDR Stress Test Tool Fails

Question asked by weiqing on Nov 19, 2015

Hello all,

 

I'm using the DDR Stress Test tool to optimize our DDR configuration. The tool is downloaded from: i.MX6/7 DDR Stress Test Tool V2.70 .

The U-Boot is already up and running, the Stress test tool is loaded via U-Boot and executed.

 

The tool runs success on the board with i.MX6 quad + 2GB memory.

It fails to run on the board with i.MX6 dual + 1GB memory, and the board with i.MX6 solo + 1GB memory.

The error message show:

"Starting DQS gating calibration

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values. "

a complete log is attached.

 

 

The binary used for testing is:

i.MX6 quad  :  ddr-test-uboot-jtag-mx6dq.bin

i.MX6 dual   :  ddr-test-uboot-jtag-mx6dq.bin

i.MX6 solo   :   ddr-test-uboot-jtag-mx6dl.bin

Am I using the correct binary file?

 

 

2) Repeating the DDR Stress Test, the results are different, then how should I use this tool?

e.g.: test on i.MX6 dual + 1GB memory:

1st run:

   MMDC registers updated from calibration

 

   Write leveling calibration

   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00010001

   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00010001

 

   Read DQS Gating calibration

   MPDGCTRL0 PHY0 (0x021b083c) = 0x43300330

   MPDGCTRL1 PHY0 (0x021b0840) = 0x03300330

 

   Read calibration

   MPRDDLCTL PHY0 (0x021b0848) = 0x40303638

 

   Write calibration

   MPWRDLCTL PHY0 (0x021b0850) = 0x3A3C423C

 

2nd run

   MMDC registers updated from calibration

 

   Write leveling calibration

   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00080022

   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00460046

 

   Read DQS Gating calibration

   MPDGCTRL0 PHY0 (0x021b083c) = 0x431C034C

   MPDGCTRL1 PHY0 (0x021b0840) = 0x034C034C

 

   Read calibration

   MPRDDLCTL PHY0 (0x021b0848) = 0x40323438

 

   Write calibration

   MPWRDLCTL PHY0 (0x021b0850) = 0x3C34423E

 

3rd run

   MMDC registers updated from calibration

 

   Write leveling calibration

   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00010001

   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00010001

 

   Read DQS Gating calibration

   MPDGCTRL0 PHY0 (0x021b083c) = 0x4400033C

   MPDGCTRL1 PHY0 (0x021b0840) = 0x033C033C

 

   Read calibration

   MPRDDLCTL PHY0 (0x021b0848) = 0x4030343A

 

   Write calibration

   MPWRDLCTL PHY0 (0x021b0850) = 0x3A3C423C

 

 

Thanks,

weiqing

Original Attachment has been moved to: DDR_Stress_Test_log.txt.zip

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