I am trying to get any response from my custom board (close to SLEVK) although DDR3 instead of LPDDR2. All I want is to get U-boot working. To download u-boot to board I use, 'imx_usb'.
i.MX6SL and DDR3 Micron: 2x MT41K128M16JT-125. --> USB OTG Communication (lsusb --> Bus 001 Device 025: ID 15a2:0063 Freescale Semiconductor, Inc)
Steps I made:
- Calculate DDR3 Timings by using I.MX6DQSDL DDR3 Script Aid V0.10xlsx (attached)
- Prepare flash_header.s (attached) (and put it board->freescale->mx6sl_evk)
- build u-boot.bin
- imx_usb u-boot.bin (and here problems begin)
After those step I expect to get u-boot > prompt in serial UART1. But on any UART available I don't get any response.
(I try with several modify flash_header.s, I can get two types of response. First if I set to use DDR3:
HAB security state: development mode (0x56787856) == work item filename u-boot.bin load_size 0 bytes load_addr 0x00000000 dcd 1 clear_dcd 0 plug 1 jump_mode 2 jump_addr 0x00000000 == end work item main dcd length 1e0 sub dcd length 1dc loading binary file(u-boot.bin) to 87800000, skip=0, fsize=272b4 type=aa out err=-7, last_trans=0 cnt=0x3c00 max=0x400 transferSize=0x400 retry=0
and error retry 10 times and no communication. Or if use flash_header.s oryginal form sl_evk (LPDDR2) I can get "success" but nothing appears on UART:
HAB security state: development mode (0x56787856) == work item filename u-boot.bin load_size 0 bytes load_addr 0x00000000 dcd 1 clear_dcd 0 plug 1 jump_mode 2 jump_addr 0x00000000 == end work item main dcd length 248 sub dcd length 244 loading binary file(u-boot.bin) to 87800000, skip=0, fsize=27134 type=aa <<<160052, 160052 bytes>>> succeeded (status 0x88888888) jumping to 0x87800400
I also check my board by using Freescale DDR Stress Tester 2.2 and attach logs. I can download configuration form board. I can even launch stress test/calibration and get some results. But no matter what I try to do no communication on UART...
Any hints/reasons why I can't get any response? Where to search?
Original Attachment has been moved to: ddr_calibration_20151117-15'1'37.log.zip
Original Attachment has been moved to: ddr_stresstest_20151118-15'4'25.log.zip