Refer to "19 DDR Calibration Code Examples" in AN4467 i.MX 6 Series DDR Calibration, Rev. 2.
Code examples in this section are for 64 bit of DDR data (1 channel 64-bits DDR3, 2 channels 32-bits LPDDR2).
My customer is using 1 channel 64-bits DDR3 with i.MX6DQ.
Next, refer to the below code in "19.2 DDR3 DQS Gating, Write and Read Delay Code Example".
// Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0)
// in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the write access.
reg32setbit((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET), 0);
while(reg32_read((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET)) & 0x00000001);
Finally, refer to "44.12.68 MMDC PHY SW Dummy Access Register (MMDCx_MPSWDAR0)" in IMX6DQRM(Rev.3).
For Channel 0: All
For Channel 1: DDR3_x64, LP2_2ch_x16, LP2_2ch_x32
In case of DDR3 64 bit access, is it necessary to set "SW_DUMMY_WR" for both of Channel 0 and 1?
(I think that it doesn't need. User should set it only for Channel 0.)
I have understood as the following about MMDCx_MPSWDAR register.
- MMDCx_MPSWDAR[1:0] for channel 0
- MMDCx_MPSWDAR[5:2] for channel 0 & 1 : DDR3_x64
Is my understanding right?