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SDRAM problems when flash is read-protected

Question asked by Carlos Garcia on Nov 13, 2015
Latest reply on Nov 16, 2015 by Carlos Garcia

Hi guys!

 

I'm using a Tower with Kinetis K65, and I managed some time ago to configure SDRAM and use it with not too much problems, but today I faced a very very strange issue.

Everything works fine when FTFE_FSEC is 0xFE, but when I change SEC bits to != 0b10, the device doesn't boots up.

Of course, under this circumstance I can't debug, as on-board flash is read-protected. After several tests, I found that when I disable the SDRAM initialization, the device works fine.

 

Anyone has seen something similar before? Can you give any indication of what can be wrong?

 

I have tested several combinations of FTFE_FSEC[SEC] bits. No positive results when flash external read is disbled.

This is my latest setting (in startup_MK65F18.S) :

/* Flash Configuration */

    .section .FlashConfig, "a"

    .long 0xFFFFFFFF

    .long 0xFFFFFFFF

    .long 0xFFFFFFFF

    .long 0xFFFFFFBF

 

I'm using KDS with MQX. SDRAM configuration is done with ProcessorExpert (and it works fine when FTFE_FSEC[SEC] == 0b10)

 

Thank you in advance

 

EDIT: Device is able to boot (although SDRAM is not working) when I comment this two lines in SDRAM_Init.c

  /* Write to an appropriate SDRAM address generates the pall command to the SDRAM block */

  //*((uint8_t *)CS0_SDRAM_BASE_ADDRESS) = 0x00U;

and

  /* Write access to the SDRAM address space generates the MRS command to that SDRAM */

  //*((uint32_t *)CS0_MRS_COMMAND_ADDRESS) = 0x00000000U;

 

It seems that this two lines are attempting to write to SDRAM address, and I suspect that this is causing any kind of CPU fault.

It's very strange... when I set FTFE_FSEC[SEC] to 0b10 everything works just fine...

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