ERR_DETECT register in MPC8555's DDR Controller.

[dijo]

Hi Pavel,

Thanks for the clear answer. And the link.

Needed little more clarification. w.r.t to the below note in the supplied link.

To summarize, the entire sequence for initialization of DDR ECC is as follows:

1. Enable ECC by setting DDR_SDRAM_CFG[ECC_EN] = 1.

2. Disable ECC error reporting (MBED = 1 and SBED = 1) in the ERR_DISABLE register.

3. Write dummy data to the entire DDR memory to initialize the ECC syndrome bits.

4. Enable ECC error reporting via ERR_DISABLE[MBED,SBED] = 00.

I couldn't get the significance of step 3. - (writing dummy data to whole of memory). Can you help understand?

Also, in a related context,

• We have marked some parts of our RAM as persistent, and hence we will never overwrite the contents.
  • What will be the impact in case we want to enable ECC in such a system.
• Also, w.r.t. memory into which another device can DMA, is there a possibility of ECC detecting errors, if the read from PQ3 is done asynchronously w.r.t the DMA transfer.

Thanks

Dijo

[LPP · Accepted solution]

>writing dummy data to whole of memory

After power up, the memory contains garbage data. ECC syndrome bits are random and thus any acces to the memory would result in ECC error. ECC bits are written by the DDR controller during writes. In order to initialize ECC syndrome bits, you should perform write to all memory locations. Actual data written is not important.

>we will never overwrite the contents

If ECC is enabled, the memory must be written at least once.

>... device can DMA, is there a possibility of ECC detecting errors

Yes. ECC errors can be detected for accesses from any master (core, DMA, PCI..,).

ECC error capture registes are provided to determine the transaction source, address and type (CAPTURE_ADDRESS, CAPTURE_ATTRIBUTES).

In case of multi-bit error, DMA halts by setting SRn[TE] and generates an interrupt if it is enabled.

[dijo]

Thanks Pavel.

Points related to dummy write is clear.

Regarding DMA, feel I didn't convey the question correctly.

Basically, we have a PCI inbound window to region in RAM using which DSP writes.

If we try to read from the core, the same memory, while it's not fully written(Not sure. Is it a possible scenario?), can we see a ECC error?