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ERR_DETECT register in MPC8555's DDR Controller.

Question asked by Dijo John Manavalan on Nov 10, 2015
Latest reply on Nov 10, 2015 by Dijo John Manavalan
Branched from an earlier discussion

Hi Pavel,

Thanks for the clear answer. And the link.


Needed little more clarification. w.r.t to the below note in the supplied link.

To summarize, the entire sequence for initialization of DDR ECC is as follows:

1. Enable ECC by setting DDR_SDRAM_CFG[ECC_EN] = 1.

2. Disable ECC error reporting (MBED = 1 and SBED = 1) in the ERR_DISABLE register.

3. Write dummy data to the entire DDR memory to initialize the ECC syndrome bits.

4. Enable ECC error reporting via ERR_DISABLE[MBED,SBED] = 00.


I couldn't get the significance of step 3. - (writing dummy data to whole of memory). Can you help understand?


Also, in a related context,

  • We have marked some parts of our RAM as persistent, and hence we will never overwrite the contents.
    • What will be the impact in case we want to enable ECC in such a system.
  • Also, w.r.t. memory into which another device can DMA, is there a possibility of ECC detecting errors, if the read from PQ3 is done asynchronously w.r.t the DMA transfer.