AnsweredAssumed Answered

Who reset IPU_CH_BUF0_RDY0/IPU_CH_BUF1_RDY0 in IMX6

Question asked by Ivy Liu on Nov 10, 2015
Latest reply on Dec 31, 2015 by Ivy Liu

Hi All,

 

I have a video path CSI0->SMFC->CH0->CH11->IC->CH22->CH23->DMFC->DP->DC->DI0.

But I only can get one frame displayed.

 

It looks like that after this display, the buffer for channel 0 and 22 are not ready.

When I mannually reset register IPU_CH_BUF0_RDY0 and IPU_CH_BUF1_RDY0 for all 4 channels, I will get another frame.

 

I think there is something wrong with my IPU setting.

Could someone help to explain which setting or who in IPU will clear/reset Registers IPU_CH_BUF0/1_RDY0/1 automaticaly?

 

 

Best Regards,

Ivy

Outcomes