For the MCF52235 at 60 MHz instructions seem to be executing much slower than expected.
I don't have much experience with the ColdFire V2 core and could use some help.
My configuration is an external 25 MHz crystal and then the PLL configured for a 60 MHz system frequency.
The CCHR register is 0x04, so divide external crystal oscillator by 5.
The MFD bits are 100, and RFD bits are 000.
So the system clock should be 25MHz / 5 * 12/1 = 60 MHz.
And indeed the configuration seems correct because the measured CLKOUT signal (pin 1) is 16.6 nsec.
But the instruction execution time looks too slow when a output pin is toggled with know instructions in between.
For example: (See the attached C and assembly code)
1) Set output pin high,
2) Execute five trap (trapf) assembly instruction, (1 cycle instruction used instead of NOPs)
3) Set output pin low.
The measured time for the pin to toggle is ~9 uSec.
Based on a 16.6 nSec clock and the number of cycle used between toggling the pin, I would expect the execution time to be well below 200 nsec.
I've tested the timing using the trap, and also with NOPs. Both gave basically the same execution time.
I don't think the processor is getting interrupted between setting the output pin high and then low. The last test I did was to put the test in the pit1ISR and the timing was the same.
Please see the attached code and my clock settings.
Do you agree 9 usec in much too long?
Any ideas what might be causing the problem or how to narrow it down?