Hi,

We've used "efsctsi" assembly instruction on MPC5xxx MCU and "fctiw" on MPC83xx PowerQUICC II Pro CPU (having SPEFSCR[FRMC] / FPSCR[RN] = 00 (round to nearest)) and we were surprised of the result. We were expecting the following 32bits floats to be converted to the following integers:

. 6.5 -> expected=7 ; obtained=6

. 7.5 -> expected=8 (obtained that)

. 8.5 -> expected=9 ; obtained=8

. -6.5 -> expected = -7 ; obtained = -6

. -7.5 -> expected = -8 (obtained that)

. -8.5 -> expected = -9 ; obtained = -8

So, is it possible to use these instructions to round floats to integer including round +x.5 to x+1 and -x.5 to -x-1? Or are these instructions performing a base-2 rounding rather than a base-10 rounding?

Thanks.

I can confirm observed behavior. I have test with e200z759. It is mode "Round to nearest, ties to even" and it seems to be fixed on this core.

IEEE floating point - Wikipedia, the free encyclopedia

e200z760 has following SPEFSCR[RM] affecting rounding mode. Note that FRMC bit also influence float to integer rounding behavior so here you should be able to configure all options from table above.