Useful link: Error Correction and Error Handling on PowerQUICC III Processors
http://www.freescale.com/files/32bit/doc/app_note/AN3532.pdf
Memory select error is set if a LAW maoss an access address to DDR but the address doesn't hit any valid chip select space defined by the DDR memory bounds registers.
DDR ECC hardware is capable of correcting single-bit errors and detecting mlti-bit errors.
Multi-bit error sets ERR_DETECT[MBE] and causes exception to the core.
Single-bit error is corrected by the hardware and ERR_SBE[SBEC] counter is increased. This error is not visible to software unless the counter reaches the threshold ERR_SBE[SBET]. In this case, ERR_DETECT[SBE] is set and exception can be risen.
Multiple memory error bit ERR_DETECT[MME] will be set if ERR_DETECT[SBE] is already set a new SBE event happens.
ECC detects errors when data are read from the DDR memory. It detects data corruption in RAM.
Have a great day,
Pavel
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