RCW U-boot print and P4080 QorIQ Multicore Communication Processor Reference Manual

[drewboudreau]

I am having a hard time reconciling USDPAA documentation and the P4080 Processor Reference Manual in regards to RCW.  The SRA user manual listed the following as a valid RCW for two x4 SRIO ports:

00000000: aa55 aa55 010e 0100 105a 0000 0000 0000

00000010: 1e1e 181e 0000 cccc 5840 0000 3c3c 2000

00000020: fe80 0000 e100 0000 0000 0000 0000 0000

00000030: 0000 0000 008b 6000 0000 0000 0000 0000

00000040: 0000 0000 0000 0000 0813 8040 532a bb17

This looks like 640 bytes not the 512.  SRIO Driver documentation in the QorIQ SDK documentation shows:

00000000: 105a0000 00000000 1e1e181e 0000cccc

00000010: 58400000 3c3c2000 fe800000 e1000000

00000020: 00000000 00000000 00000000 008b6000

00000030: 00000000 00000000 00000000 00000000

Okay at least 512 bits now...

Section 4.6.4.1 of the Processor reference manual list bits 128-133 as the SRDS_PRTCL bits.  Table 3-16 says for two x4 SRIO ports valid SRDS_PRTCL values are 0x13, 0x16, 0x19.  This overlaps reserved bits 134 and 135.

What am I missing?  I am currently running an XES SBC and have run the SRA demo app with a loopback.  The device is running at 2.5 Gbps and I want to know what the RCW setting is.  The loopback cable is not ideal.  Does SRIO link train like PCIe?  If the cable can't support BW will it drop to lower speed?  What am I missing on the RCW setting in the Manual/QorIQ SDK documentation?  Thanks so much!!

[adeel]

Hi,

The Freescale Manual always show RCW with starting 8 bytes header which is necessary when flashing RCW to flash memory. The U-Boot startup RCW printout doesn't print those starting 8 bytes header. The rest of the RCW is exactly the same and the last bytes are checksum which is also not printed.

The SRA application will not run on P4080 because the SRIO driver occupied the SRIO ports and because of that SRA can't use them. Could you describe your setup? I don't know what is XES SBC. If you have a loopback between two SRIO ports then the first thing you should check whether link is established.

- Adeel

What am I missing?  I am currently running an XES SBC and have run the SRA demo app with a loopback.  The device is running at 2.5 Gbps and I want to know what the RCW setting is.  The loopback cable is not ideal.  Does SRIO link train like PCIe?  If the cable can't support BW will it drop to lower speed?  What am I missing on the RCW setting in the Manual/QorIQ SDK documentation?  Thanks so much!!

[drewboudreau]

Adeel,

We loaded the UIO SRIO driver from Freescale instead of the default Linux SRIO driver, this allowed the operation of SRA.  We initially loaded the Linux SRIO drivers and yes SRA app would crash.  Uboot shows the x1 link on the two ports.  This was achieved with a simple loopback cable.  XES is a manufacturer of Single Board Computers (SBC). 

The application seems to run fine.  We can due memory transfers, the windows look right, everything appears to work.   

[addiyi]

The easy way to handle RCW is use of PreBootLoader part of QCVS​. PreBootLoader is license free and provide support for almost all QorIQ processors.

Adrian

[drewboudreau · Accepted solution]

I tracked down my confusion.  In the P4080 Processor Reference Manual the SRDS_PRTCL values are listed as 8 bit numbers, when in actuality since they apply to 6 bits the 2 MSB are dropped.