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Flexbus Bus cycle Question

Question asked by JIM MORRIS on Oct 30, 2015
Latest reply on Jan 14, 2016 by JIM MORRIS

I have some issues that are leading me to believe that the Flexbus Appnote for the Kinetis processors and the descriptions in the data sheets are not telling me the entire store.

 

To make a long story short, I have a design where I need to interface My MK10FN1M0VLQ12 K10 micro controller with a memory mapped device in 16-bit mode, with the device having 16 directly accessible 16-bit registers.  I have that working using the multiplexed AD signals, such that FB_AD[3:0] are tied to ADDR[3:0] on my device, FB_AD[32:16] are tied to DATA[15:0] of my device, and the FB_OE#, FB_CS0# and FB_RW are used to properly generate the signals the device expects for read and write operations.  The device has an ACK# signal which drives back to FB_TA# on my K10 micro controller.

 

I am then memory mapping the device in C as uint16_t pointers, like this:

 

// Setup base address of device

const uint32_t mydevice_base_addr = 0x60000000;

 

// Setup register pointers

mydevice_register_A = (uint16_t *) (mydevice_base_addr + 0x0);

mydevice_register_B = (uint16_t *) (mydevice_base_addr + 0x1);

mydevice_register_C = (uint16_t *) (mydevice_base_addr + 0x2);

mydevice_register_D = (uint16_t *) (mydevice_base_addr + 0x3);

 

And so on.....

 

I am using Processor Expert, and have the CS0# of the Processor component set to be 16-bit for the port width, and so on.

 

What I am seeing  happen as I go on through trying to initialize my device, using a logic analyzer to watch the bus, is that while things SEEM to work on the surface, is that any access to an EVEN register on the device works as expected. I will see a single 16-bit read or write bus cycle.  However, ANY access at all to an ODD register appears to result in the expected access, followed by an access to the next register up. For example, single step the code in KDS with a write the register at 0x0 will result in a SINGLE write to the bus.  I get one chip select cycle on the Flexbus on the logic analyzer.  However, if I attempt to write (or read) a ODD address such as offset 0x1, I get TWO bus cycles generated by the K10.  I'll get the expected cycle to 0x1, followed by a cycle to 0x2.

 

Unfortunately, the end result is that I cannot configure and use my memory mapped device properly. It has specific sequences that require for example that I write registers 0xD 0xE and 0xF with specific values in a specific sequence.  When I do those 3 writes, I get a write to 0xD followed by a write to 0xE, a write to 0xE (the next line of code), then a write to 0xF followed by a write to 0x0.  I've gone so far as to do inline __asm() to test this, using the STRH operation, which should move a half word, and still get this behavior.

 

So the question is, does the Kinetis and/or KDS prevent single 16-bit port accesses on the Flexbus, even when the Flexbus is set to LEFT ALIGNED 16-bit bus width?  Why does it work for even and not for odd addresses?

 

How can I resolve this? I know a PCB change may be required, but the question is, can I avoid requiring external address latches and right aligning the data?  Right now I feel like going to full 32-bit bus, with AD[3:0] for the address (latched) and AD[15:0] for the data, with the port width set to 32-bits, but with the bits AD[31:16] not tied to anything, MIGHT fix this, but am not going to spend the money on that level of change until I understand fully the issue and the resolution.

 

Thanks!

Jim Morris

Huntsville, Alabama

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