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MK20DX256 SPI phase setting not correct

Question asked by Erik Iverson on Oct 28, 2015

Good day, I am trying to configure an MK20DX256 microcontroller as an SPI slave. The microcontroller is on the Teensy 3.2 board. Since the wiring framework (arduino-like language) doesn't support SPI slave mode, I am looking at the freescale documentation, which is a document labelled K20P64M72SF1RM. The master I am using is a TI C28 core, that is configured for continuous clocking (SPI enable/chip select stays low across multiple bytes transferred), the clock is active high, and the phase setting is such that on the data is sampled on rising edges, and changes on falling edges. In this particular TI parlance, this is clock polarity 0, phase polarity 1. However, I see that figure 45-71 on page 1154 of the aforementioned freescale documentation, this translates to clock polarity 0 and phase polarity 0. That's all fine, but I am not seeing this behavior on the SPI MISO line. I am attaching a screenshot that shows the MK20DX256 SPI slave changing on all rising edges. I have read the datasheet and am not sure what I am missing. When I change the phase to 1 on the freescale part, it still changes on rising edges, but according to the data sheet, this is correct.


Also, I can see valid data with a logic analyzer, but all the values popped from the RXFIFO are zero. This may be a separate issue though. My code is attached. Thanks. -ErikimageFile.png

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