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请问 MKL26 DMA从内存发送到UART1的发布出去的问题

Question asked by bi shihao on Oct 28, 2015
Latest reply on Oct 29, 2015 by Alice_Yang

大家好,我用DMA方式把内存上数组从uart0上发送出去可以,但是改到uart1上出现了dma busy的错误,发不出去。

uart0 Transmit具有Async DMA capable,uart1 Transmit没有Async DMA capable,这个Async DMA capable怎么解释?

需要怎么配置DMA才能从Uart1发送出去。

 

DMA的配置如下

#define DMA0_DESTINATION  0x4006B007        /* the memory adress of UART1_D register */   

 

#define DMA0_SOURCE_ADDR  (uint32_t)testdata  /* define the source data array address */   

/* array to be sended */

uint8_t testdata[]={"\nFreescale Kinetis KL16\n"};

void DMA0_init(void)

{

 

  /* Enable Clock gating for the DMA and DMA MUX */

  SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;

  SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;

 

  /* Create pointer & variable for reading DMA_DSR register */

  volatile uint32_t* dma_dsr_bcr0_reg = &DMA_DSR_BCR0;

  uint32_t dma_dsr_bcr0_val = *dma_dsr_bcr0_reg;

 

  DMAMUX0_CHCFG0 = 0x00;   //Disable DMA MUX channel first

 

  /* Check for pending erors and/or the done bit */

  if (((dma_dsr_bcr0_val & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)

      | ((dma_dsr_bcr0_val & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)

      | ((dma_dsr_bcr0_val & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)

      | ((dma_dsr_bcr0_val & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))

    DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK;     //Clear pending erors and/or the done bit

 

 

  DMA_SAR0 = DMA0_SOURCE_ADDR;                                  //Set source address to UART0_D REG

 

  DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(sizeof(testdata));             //Set BCR to know how many bytes to transfer

 

  DMA_DCR0 &= ~(DMA_DCR_SSIZE_MASK | DMA_DCR_DSIZE_MASK);       //Clear source size and destination size fields

 

  /* Set DMA as follows:

         Source size is 8-bit size

         Destination size is 8-bit size

         Cycle steal mode

         External requests are enabled

         source address increments 1 automatically

  */

 

  DMA_DCR0 |= (DMA_DCR_SSIZE(1)

               | DMA_DCR_DSIZE(1)

               | DMA_DCR_CS_MASK 

               | DMA_DCR_ERQ_MASK

               | DMA_DCR_EINT_MASK

               | DMA_DCR_SINC_MASK);

 

 

  DMA_DAR0 = DMA0_DESTINATION;    //Set source address to UART1_D REG

 

  DMAMUX0_CHCFG0 = DMAMUX_CHCFG_SOURCE(5);   //Select UART1 TX as channel source

 

  DMA_DCR0 |= DMA_DCR_START_MASK;

 

  DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;   //Enable the DMA MUX channel

 

}

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