I have a project that use IMX6D EIM interface to communicate with FPGA， I have configured the EIM timing as:
1. synchronous read/write mode
2. MUM = 1, DSZ = 001, that is Multiplexed Address/Data mode and Data width is 16 bit。
When I read or write the EIM interface, The FPGA side sampling the bus signal with chip scope. We found that the address is increased by four, for example:
0x00, 0x04, 0x08, 0x0C, 0x10, ......
That is confused, the data width is 16, address bus should increased by 2, why is 4?
anyone can help me?