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About I2S/ESAI sampling rate in i.MX6DQ.

Question asked by Keita Nagashima on Oct 26, 2015
Latest reply on Nov 12, 2015 by Yuri Muhin

Dear All,

 

Hello. I have a question about I2S/ESAI sampling rate in i.MX6DQ.

Refer to "61.1.1 Features" in IMX6DQRM(Rev.3).

=========

Programmable I2S modes (Master, Slave or Normal). Maximum audio sampling rate

is 196kHz. (Note that maximum sampling rate depends on IPG frequency.)

=========

 

I calculated the bit clock from Data sheet spec.

Refer to "Table 86. SSI Transmitter Timing with Internal Clock" in IMX6DQAEC(Rev.4).

- SS1: AUDx_TXC/AUDx_RXC clock period = 81.4[ns]

 

- Bit clock = 1/81.4 [ns] = 12.285 [MHz]

- Max sampling frequency = 12.285 [MHz] / 64 = 191.95 [kHz]

  --> 191.95 [kHz] < 196 [kHz]

 

[Q1]

I think that max bit clock = 12.288 [MHz].

So, the AUDx_TXC/AUDx_RXC clock period will be "81.38 [ns]"

Is this a rounding error?

 

[Q2]

If Q1 is yes, Max sampling frequency will be 192 [kHz].

Does i.MX6DQ support to 196 [kHz]?

 

[Q3]

What is the meaning of "Note that maximum sampling rate depends on IPG frequency."

I didn't understand well.

 

Best Regards,

Keita

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