Hello. I have a question about Power sequence in i.MX6SL.
Refer to Table 7-3. Power sequence in Hardware Development Guide for i.MX 6SoloLite Applications Processor, Rev. 1.
There are two kind of power sequence at the Using all internal LDOs and Bypassed.
At the time of Power sequence, does the internal LDOs become invalid?
(Why are there two kind of sequence?)
Which correct description Data sheet or Hardware Design Guide?
(Description in Hardware Design Guide was hard requirement.)