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MPC5674F - DMA seems to mix up addresses internally?

Question asked by Benedikt Schmied on Oct 23, 2015
Latest reply on Oct 26, 2015 by Lukas Zadrapa

Hey there,


We are using the DMA controller intensively for multiple XBAR - slaves such as ETPU, EQADC, SIU and DSPI. Especially for the EQADC and DSPI slaves we encounter similiar problems. When load increases on the XBAR, e.g. the processor and the DMA both try to read / write from slaves, the SPI may push data to the SRAM (RX - path) which is not physically measurable. As we are using the scatter-gather capability, the problems seems to be solved for the next DMA - request. Unfortunately, the application may shut down the whole Engine Control Unit in case of illegal data. Of course, we are still searching for improper steps the firmware takes to initialize the controller, but for the time being, we have not found anything.

The masters' priorities for slave 6 and 7 (Peripheral Bus A and B) has been changed in order to favor both eDMA controllers. Different priority settings for the eDMA controller have already been attempted, but nothing seems to solve our problem so far.

We are using the MPC5674F controller.

Additionally, prefetching is enabled as well as an external SRAM is attached to the EBI.

Is there any known issue concerning high load and eDMA transfers? Unfortunately, we will start commissioning shortly, so I just wanted to ask, whether we may have to watch out for particular settings.


Thanks for your help.