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No data from CSI0 parallel camera MT9P031

Question asked by James CHUNG on Oct 22, 2015
Latest reply on Nov 20, 2015 by Hu Donghong

Hi

 

I am in trouble to enable MT9P031 to CSI0 parallel port.

I can see all clocks like PIXCLK, HSYNC and VSYNC, but there is no SYNC interrupt.

 

I think I tried most ways in the community, but no luck yet.

 

So,

1) Please let me know how to check whether hardware receives clocks (e.g, pixel clock, hsync or vsync)?

    I couldn't find status registers in CSI

 

2) I've checked data path from CSI, SMFC, IDMAC, ... eventually memory.

   But, I didn't know which path is wrong. Do you have any way to figure out the problem?

 

NOTE: I don't use mclk. Camera has a clock.

 

Thanks in advance.

 

James

 

================== This is a log from my debugging environment ============

./jj
Hi James.... G16
In MVC: mxc_v4l_open

   device name is Mxc Camera
   clock_curr=mclk=24000000
End of mxc_v4l_open: v2f pix widthxheight 640 x 480
End of mxc_v4l_open: crop_bounds widthxheight 640 x 480
End of mxc_v4l_open: crop_defrect widthxheight 640 x 480
End of mxc_v4l_open: crop_current widthxheight 640 x 480
On Open: Input to ipu size is 640 x 480
james======== check2-b
james ok1
#### ipu Vsync=1 Hsync=0 Ext=0 pix=0 dat_en=0 FMT=3
clk_mode=0
CSI_SENS_CONF = 0x00000B01
CSI_ACT_FRM_SIZE = 0x01DF027F
mt9p031 power on 0
James 11 init.... check....
   Setting mclk to 24 MHz
mode is 0 1 0
xres=640 yres=480 frame=1

==== This is I2C registers for MT9P031.... and I can see power and clock are good.
james write: 1 0x0040
james write: 2 0x0010
james write: 3 0x01df
james write: 4 0x027f
james write: 35 0x0000
james write: 34 0x0000
james write: 5 0x008e
james write: 6 0x0019
james write: 8 0x0000
james write: 9 0x00c8
james write: 7 0x1f82
james write: 16 0x0051
james write: 17 0x1c01
james write: 18 0x000d
james write: 16 0x0053
james Setup done 0
In MVC:mxc_v4l_ioctl
In MVC: mxc_v4l_do_ioctl c0cc5616
   case VIDIOC_S_PARM
In mxc_v4l2_s_param
james g_parm........#########
   Current capabilities are 1001
   Current capturemode is 0  change to 0
   Current framerate is 30  change to 30
mt9p031 power on 1
james $$$$$$$$$ s_param
mode is 0 1 0
xres=640 yres=480 frame=1
james write: 1 0x0040
james write: 2 0x0010
james write: 3 0x01df
james write: 4 0x027f
james write: 35 0x0000
james write: 34 0x0000
james write: 5 0x008e
james write: 6 0x0019
james write: 8 0x0000
james write: 9 0x00c8
james write: 7 0x1f82
james write: 16 0x0051
james write: 17 0x1c01
james write: 18 0x000d
james write: 16 0x0053
james Setup done 0
   clock_curr=mclk=24000000
   clock_curr=mclk=24000000
james : set GATED_CLK
#### james Vsync=0 Hsync=0 Ext=1 pixclk=0 dat_en = 0
   g_fmt_cap returns widthxheight of input as 640 x 480
james======== check1
james======== check2-b
james ok1
#### ipu Vsync=0 Hsync=1 Ext=1 pix=0 dat_en=0 FMT=3
clk_mode=0
CSI_SENS_CONF = 0x00008B02
CSI_ACT_FRM_SIZE = 0x01DF027F
james======== check2
In MVC:mxc_v4l_ioctl
In MVC: mxc_v4l_do_ioctl 4014563c
   case VIDIOC_S_CROP
   Cropping Input to ipu size 640 x 480
In MVC:mxc_v4l_ioctl
In MVC: mxc_v4l_do_ioctl c0cc5605
   case VIDIOC_S_FMT
In MVC: mxc_v4l2_s_fmt
   type=V4L2_BUF_TYPE_VIDEO_CAPTURE
End of mxc_v4l2_s_fmt: v2f pix widthxheight 640 x 480
End of mxc_v4l2_s_fmt: crop_bounds widthxheight 640 x 480
End of mxc_v4l2_s_fmt: crop_defrect widthxheight 640 x 480
End of mxc_v4l2_s_fmt: crop_current widthxheight 640 x 480
In MVC:mxc_v4l_ioctl
In MVC: mxc_v4l_do_ioctl c0cc5604
   case VIDIOC_G_FMT
In MVC: mxc_v4l2_g_fmt type=1
   type is V4L2_BUF_TYPE_VIDEO_CAPTURE
End of mxc_v4l2_g_fmt: v2f pix widthxheight 640 x 480
End of mxc_v4l2_g_fmt: crop_bounds widthxheight 640 x 480
End of mxc_v4l2_g_fmt: crop_defrect widthxheight 640 x 480
End of mxc_v4l2_g_fmt: crop_current widthxheight 640 x 480
  Width = 640
  Height = 480
  Image size = 307200
  Pixel format = GREY
######## virual ac100000 ac180000
james A: 0 0 0 0
IPU_INT_STAT(5) = 0x0
IPU_INT_STAT(6) = 0x0
IPU_INT_STAT(7) = 0x800000
IPU_INT_STAT(8) = 0x0
IPU_INT_STAT(9) = 0x0
IPU_INT_STAT(10) = 0x0
IPU_SRM_STAT=0
IPU_PROC=0
IPU_DISP=0
IC_CONF=40000000
imx-ipuv3 2400000.ipu: init channel = 15
james init s1
SMFC************* 0x0
csi_init 268435392 0
csi_init 268435392 0 new 0x4008b02
James TODO: enable clk
imx-ipuv3 2400000.ipu: ipu busfreq high requst.
imx-ipuv3 2400000.ipu: IPU_CONF =  0x00000660
imx-ipuv3 2400000.ipu: IDMAC_CONF =  0x0000002F
imx-ipuv3 2400000.ipu: IDMAC_CHA_EN1 =  0x00800000
imx-ipuv3 2400000.ipu: IDMAC_CHA_EN2 =  0x00000000
imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI1 =  0x18800001
imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI2 =  0x00000000
imx-ipuv3 2400000.ipu: IDMAC_BAND_EN1 =  0x00000000
imx-ipuv3 2400000.ipu: IDMAC_BAND_EN2 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL0 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL1 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL0 =  0x00800000
imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL1 =  0x00000000
imx-ipuv3 2400000.ipu: DMFC_WR_CHAN =  0x00000090
imx-ipuv3 2400000.ipu: DMFC_WR_CHAN_DEF =  0x202020F6
imx-ipuv3 2400000.ipu: DMFC_DP_CHAN =  0x000096D4
imx-ipuv3 2400000.ipu: DMFC_DP_CHAN_DEF =  0x2020F6F6
imx-ipuv3 2400000.ipu: DMFC_IC_CTRL =  0x00000002
imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW1 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW2 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW3 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_FS_DISP_FLOW1 =  0x00000000
imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_FSIZE =  0x00000000
imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_C =  0x00000000
imx-ipuv3 2400000.ipu: IPU_IC_CONF =  0x40000000
can you see ok
ok-11-1
imx-ipuv3 2400000.ipu: initializing idma ch 0 @ c08c0000
imx-ipuv3 2400000.ipu: ch 0 word 0 - 00000000 00000000 00000000 E0001800 00077C4F
imx-ipuv3 2400000.ipu: ch 0 word 1 - 07820000 00F06000 00C7C000 00009FC0 00000000
imx-ipuv3 2400000.ipu: PFS 0x6,
imx-ipuv3 2400000.ipu: BPP 0x3,
imx-ipuv3 2400000.ipu: NPB 0x1f
imx-ipuv3 2400000.ipu: FW 639,
imx-ipuv3 2400000.ipu: FH 479,
imx-ipuv3 2400000.ipu: EBA0 0x3c100000
imx-ipuv3 2400000.ipu: EBA1 0x3c180000
imx-ipuv3 2400000.ipu: Stride 639
imx-ipuv3 2400000.ipu: scan_order 0
imx-ipuv3 2400000.ipu: uv_stride 0
imx-ipuv3 2400000.ipu: u_offset 0x0
imx-ipuv3 2400000.ipu: v_offset 0x0
imx-ipuv3 2400000.ipu: Width0 0+1,
imx-ipuv3 2400000.ipu: Width1 0+1,
imx-ipuv3 2400000.ipu: Width2 0+1,
imx-ipuv3 2400000.ipu: Width3 0+1,
imx-ipuv3 2400000.ipu: Offset0 0,
imx-ipuv3 2400000.ipu: Offset1 0,
imx-ipuv3 2400000.ipu: Offset2 0,
imx-ipuv3 2400000.ipu: Offset3 0
ipu_conf =0x660
ipu=0x760
>>>>>>>>>>>>> ipu enables csi 0
reg ipu conf 760
IPU_CONF=761, 1
IPU_INT_STAT(5) = 0x0
IPU_INT_STAT(6) = 0x0
IPU_INT_STAT(7) = 0x800000
IPU_INT_STAT(8) = 0x0
IPU_INT_STAT(9) = 0x0
IPU_INT_STAT(10) = 0x0
IPU_SRM_STAT=0
IPU_PROC=0
IPU_DISP=0
IC_CONF=40000000
IPU_INT_STAT(5) = 0x0
IPU_INT_STAT(6) = 0x0
IPU_INT_STAT(7) = 0x800000
IPU_INT_STAT(8) = 0x0
IPU_INT_STAT(9) = 0x0
IPU_INT_STAT(10) = 0x0
IPU_SRM_STAT=0
IPU_PROC=0
IPU_DISP=0
IC_CONF=40000000
ERROR: v4l2 capture: mxc_v4l_read timeout counter 0
James still stop
imx-ipuv3 2400000.ipu: CSI stop timeout - 5 * 10ms
>>>>>>>>>>>>> ipu disables csi 0, 0, 0x760
imx-ipuv3 2400000.ipu: ipu busfreq high release.
v4l2 read error.In MVC:mxc_v4l_close

mt9p031 power off 1
mxc_v4l_close: release resource
MVC: In mxc_free_frame_buf
In MVC:mxc_free_frames
root@imx6qsabresd:~#

Outcomes