Our customer have video ADC clock frequency question.
Would you please Answer tomorrow 23 Oct, by 2015.
How many MHz speed of proc_clk input frequency of video AFE blocks .?
Refer from 9.10.13 Video ADC clock.
At frequencies below the formula is correct?
From 126.96.36.199 Typical PLL Configuration
PLL6(video PLL) PLL output=24M*44.33=1064MHz(This is PLL6main clock)
Video ADC clock=532/4=133MHz
video ADC clock divide by 2 clock=66.5MHz
From Chapter 61 61.1 Introduction of Figure 61-1. Video subsystem block diagram
data clk= 66.5MHz