I'm using the same processor as the Vybrid tower board the MVF61NS. This is the package with L1,L2 cache clocked at 500mhz. We are running our entire application bare-metal from spansion quadspi XIP (no external RAM at all). We're using a processing heavy commercial library that is a black box to us (provided as a .lib). Also we are using the ARM DS-5 development suite.
The library purportedly runs 7 times faster than the results we're getting. The supplier provided a binary to us that supports that as well but it only runs on top of the timesys Linux distro that is packaged with the tower board: I was able to run the binary on our board with linux and see the fast results which leads me to believe it is possible though we can't use Linux in our application.I have enabled caching on the quadspi section on our image and I see significant performance gains but we are still 7 times slower than running off the linux board.
I did a little bit more sleuthing to make sure that the quadspi program data was indeed being cached: Using an oscilloscope I probed the clock line on the quadspi chip during our library function calls and only see clocks during less than 5% of the time. This suggests to me that a majority of the program is already cached.
What would be the best settings for the MMU for speed running quadspi XIP?
Can anyone think of any other register settings that could need to be enabled to get a performance bump like this?
Many thanks in advance!